1 qs532805/a/b guaranteed low skew 3.3v cmos clock driver/buffer industrial temperature range july 2000 1999 integrated device technology, inc. dsc-5785/- c qs532805/a/b industrial temperature range guaranteed low skew 3.3v cmos clock driver/buffer functional block diagram oea ina inb oa5 oa1 5 5 mon ob5 ob1 oeb description the qs532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. this device offers two banks of 5 non-inverting outputs. the qs532805 incorporates 25 w series termination resistors. this clock buffer product is designed for use in high performance workstations, embedded and personal computing systems using 3v to 3.6v supply voltages. several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. the qs532805 can accept 5v input and control signals. the qs532805 is characterized for operation at -40c to +85c. features: - jedec compatible lvttl level inputs and outputs - 10 output, low skew clock signal buffer - monitor output - clock inputs are 5v tolerant - pinout and function compatible with qs5805t - 25 w on-chip resistors for low noise - input hysteresis for better noise margin - guaranteed low skew: 0.7ns output skew 0.7ns pulse skew 1ns part-to-part skew - std., a, and b speed grades (b speed in qsop package only) - available in qsop and soic packages note: qs532805 has a 25 w series termination resistor on each clock output, including monitor.
2 industrial temperature range qs532805/a/b guaranteed low skew 3.3v cmos clock driver/buffer pin configuration qsop/ soic top view 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oa 1 oa 2 oa 3 gnd a oa 4 oa 5 gndq oe a in a ob 1 ob 2 ob 3 gnd b ob 4 ob 5 mon oe b in b v cca v ccb so20-2 so20-8 absolute maximum ratings (1) symbol description max. unit v term (2) supply voltage to ground C 0.5 to +7 v dc output voltage v out C 0.5 to vcc+0.5 v v term (3) dc input voltage v in C 0.5 to +7 v v ac ac input voltage (pulse width 20ns) -3 v i out dc output current v in < 0 -20 ma dc output current max. sink current/pin 120 ma t stg storage temperature C 65 to +150 c t j junction temperature 150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vcc terminals. 3. all terminals except vcc. capacitance (t a = +25 o c, f = 1.0mhz, v in = 0v, v out = 0v) pins typ. max. (1) unit c in 46 pf c out 810 pf note: 1. this parameter is guaranteed but not production tested. recommended operating conditions symbol description min. max unit v cc power supply voltage 3 3.6 v v in input voltage 0 5.5 v v out voltage applied to outputs 0 v cc v t a ambient operating temperature C 40 85 c pin description pin names i/o description oea , oeb i output enable ina, inb i clock inputs oan , obn o clock outputs mon o monitor outputs (does not 3-state)
3 qs532805/a/b guaranteed low skew 3.3v cmos clock driver/buffer industrial temperature range dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = -40c to +85c, v cc = 3.3v 0.3v symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage guaranteed logic high for inputs 2 5.5 v v il input low voltage guaranteed logic low for inputs C0.5 0.8 v v ic clamp diode voltage (3) vcc = min., i in = -18ma C0.7 C1.2 v v oh output high voltage vcc = min., i oh = -100 m a vcc C 0.2 v vcc = min., i oh = -8ma 2.4 v v ol output low voltage vcc = min., i ol = 100 m a 0.2v vcc = min., i ol = 6ma 0.4 v vcc = min., i ol = 8ma 0.5 v i in input leakage current vcc = max., v in = vcc or gnd 1 m a i oz output leakage current vcc = max., v out = vcc or gnd 1 m a i off input power off leakage vcc = 0v, v in = vcc or gnd 1 m a i odh output high current (2) vcc = 3.3v, v in = v ih or v il , v o = 1.5v C30 C100 C200 ma i odl output low current (2) vcc = 3.3v, v in = v ih or v il , v o = 1.5v 30 100 200 ma i os short circuit current (2,3) vcc = max., v out = gnd C 60 ma r out output resistance (4) vcc = min 28 w notes: 1. typical values are at v cc = 3.3v, t a = 25c. 2. not more than one output should be used to test this high power condition. duration is less than one second. 3. guaranteed by design but not tested. 4. output resistance represents the total output impedence of the logic device and includes added series termination resistanc e. power supply characteristics symbol parameter test conditions (1) typ. (3) max. unit i cc quiescent power supply current v cc = max., v in = gnd or vcc 0.01 100 m a d i cc supply current per input high v cc = max., v in = vcc C 0.6v, f = 0mhz 0.1 30 m a i ccd dynamic power supply current per output (2) v cc = max., oea = oeb = gnd outputs toggling at 50% duty cycle 65 100 m a/mhz i c total power supply current examples (2,4) v cc = max., oea = oeb = gnd v in = gnd or vcc 3.3 5.2 ma 50% duty cycle, f i = 10mhz five outputs toggling v in = gnd or 3v 3.3 5.2 ma v cc = max., oea = oeb = gnd v in = gnd or vcc 1.8 2.9 ma 50% duty cycle, f i = 2.5mhz all outputs toggling v in = gnd or 3v 1.8 2.9 ma notes: 1. for conditions shown as min. or max., use the appropriate values specified under dc electrical characteristics. 2. guaranteed by design but not tested. c l = 0pf. 3. typical values are for reference only. conditions are v cc = 3.3v, t a = 25c. 4. i c = i cc + ( d i cc )(d h )(n i ) + i ccd (f o )(n o ) where: d h = input duty cycle n i = number of ttl high inputs at d h f o = output frequency n o = number of outputs at f o
4 industrial temperature range qs532805/a/b guaranteed low skew 3.3v cmos clock driver/buffer skew characteristics over operating range t a = -40c to +85c, v cc = 3.3v 0.3v c load = 50pf (no resistor) qs532805 qs532805a QS532805B (3) symbol parameter (1) min. max. min. max. min. max. unit t sk(01) skew between all outputs, same transition, same bank 0.7 0.7 0.7 ns t sk(02) skew between two outputs, same transition, different banks 0.9 0.9 0.9 ns t sk(p) pulse skew; skew between opposite transitions of the same output (t phl - t plh ) 1 0.7 0.5 ns t sk(t) part-to-part skew (2) 1.5 1 1 ns notes: 1. this parameter is guaranteed but not production tested. skew parameters apply to propagation delays only. 2. t sk(t) only applies to devices of the same transition, part type, temperature, power supply voltage, loading package, and speed grade . 3. the b speed grade is only available in the qsop package. switching characteristics over operating range t a = -40c to +85c, v cc = 3.3v 0.3v c load = 50pf (no resistor) qs532805 qs532805a QS532805B (4) symbol parameter (1,2) min. max. min. max. min. max. unit t plh t phl propagation delay 1.5 6.5 1.5 5.8 1.5 5.2 ns t r output rise time, 0.8v to 2v (3) 222 ns t f output fall time, 2v to 0.8v (3) 222 ns t pzl t pzh output enable time 1.5 8 1.5 8 1.5 6.5 ns t plz t pzh output disable time 1.5 7 1.5 7 1.5 6 ns notes: 1. minimums guaranteed but not production tested. 2. the propagation delay other range indicated by min. and max. specifications results from process and environmental variable s. these propagation delays do not imply limit skew. 3. this parameter is guaranteed but not production tested. 4. the b speed grade is only available in the qsop package.
5 qs532805/a/b guaranteed low skew 3.3v cmos clock driver/buffer industrial temperature range pulse generator 500 w 500 w v cc v out v in dut 50 w 50pf 6.0 v parameter tested switch position all others closed open t plz , t pzl control input enable disable 3v 1.5v 0v 3v 0v 1.5v 1.5v output normally low switch closed 0.3v 0.3v input ouput 1 3v 1.5v 0v 1.5v 1.5v ouput 2 input ouput 3v 1.5v 0v 1.5v 2.0v 0.8v input part 1 output 3v 1.5v 0v 1.5v 1.5v part 2 output input ouput a t plha 3v 1.5v 0v 1.5v 1.5v ouput b input ouput t plh t phl 3v 1.5v 0v v oh 1.5v v ol t sk(p) = t phl - t plh t sk(02) = t plhb - t plha or t phlb - t phla pulse generator for all pulses: f 1.0mhz; t f 2.5ns; t r 2.5ns v oh v ol v oh v ol t phla t sk(02) t sk(02) t plhb t phlb v oh v ol v oh v ol t sk(01) t sk(01) t sk(01) = t plh2 - t plh1 or t phl2 - t phl1 t plh1 t phl1 t plh2 t phl2 v oh v ol v oh v ol t plh t phl t r t f output normally high t pzl t plz t phz t pzh switch open t plh1 t phl1 t sk(t) t sk(t) t plh2 t phl2 t sk(t) = t plh2 - t plh1 or t phl2 - t phl1 v oh v ol v ol v oh propagation delay pulse skew t sk(p) output skew (same bank) t sk(o1) test circuits and waveforms ouput skew (different banks) t sk(o2) enable and disable times part-to-part skew t sk(t)
6 industrial temperature range qs532805/a/b guaranteed low skew 3.3v cmos clock driver/buffer ordering information corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo, quickswitch, and synchroswitch are registered trademarks of integrated device technology, inc. xxxx device type xx package q so 532805 532805a (532805b) quarter size small outline pacakge (so20-8) small outline ic (so20-2) guaranteed low skew 3.3v cmos clock driver/buffer (qsop package only) qs
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